The present invention relates to a technique for use in the manufacture of a semiconductor integrated circuit device; and more specifically, the invention relates to a technique that is effective for application to a semiconductor integrated circuit device including a short channel MIS (metal insulator semiconductor) having a gate length, i.e. the width of the gate electrode, which is less than 0.1 μm.
The film thickness of the gate insulating film in a MIS transistor having a gate length which is less than 0.07 μm is presumed to be less than 1.2 nm. However, thinning a conventionally used silicon oxide film for use in the gate insulating film will cause the leakage current to exceed 10 A/cm2, which involves an increase in the standby current, thereby creating a problem.
Accordingly, a trial has been conducted using an insulating film having a comparably high relative dielectric constant (hereunder referred to as a high dielectric constant insulating film), for example, an alumina film having a relative dielectric constant which is about 7 to 11 for the gate insulating film, and in which the effective film thickness is reduced while maintaining the physical film thickness at 1.5 nm or more. Here, the effective film thickness signifies an equivalent silicon oxide film thickness in consideration of the relative dielectric constant.
As an example, the publication IEDM (International Electron Device Meetings in an article entitled “80 nm poly-silicon gated n-FETs with ultra-thin Al2O3 gate dielectric for ULSI applications” at pp. 223-226, 2000) discloses the performance characteristic of a MIS transistor having a gate insulating film made of an alumina film, with a gate length of less than 0.1 μm.